Step-by-Step Instructions for the Capstone
1. Processor Design (November 7 – November 14)
1.
Define the Instruction Set Architecture (ISA):
· Choose a small set of RISC-style instructions (e.g., LOAD, STORE, ADD, SUB, BRANCH).
· Define formats for each instruction, specifying opcodes, operands, and encoding.
1.
Design Pipeline Stages:
· Divide the processor into five pipeline stages: Fetch (IF), Decode (ID), Execute (EX), Memory (MEM), Write-back (WB).
· Outline the function of each stage and any data it passes to the next stage.
1.
Implement Pipeline Control Logic:
· Design control signals for managing each pipeline stage.
· Add hazard detection and resolution logic for
data hazards (using techniques like forwarding and stalls) and
control hazards (such as branch prediction).
1.
Document: Create initial documentation outlining the processor architecture, pipeline stages, and hazard handling approach for inclusion in the final report.
2. Memory Hierarchy and Cache Design (November 14 – November 21)
1.
Design Main Memory:
· Set up a simple main memory model (e.g., 1KB memory), with addresses for instructions and data.
1.
Implement a Direct-Mapped Cache:
· Design a cache with specifications like:
·
Cache Size: 64 words
·
Block Size: 4 words
·
Direct Mapping: Use (Memory Address) % Number of Cache Lines to map memory blocks to cache lines.
1.
Develop Cache Access Logic:
· Write logic to check if requested data is in the cache (hit) or not (miss).
· On a miss, load a block of data from main memory to cache, simulating the miss penalty.
1.
Test Cache Configuration:
· Write small test programs to evaluate cache behavior (e.g., repetitive memory access patterns).
· Record cache hit/miss rates under different conditions.
1.
Document: Summarize cache architecture, mapping approach, and preliminary performance findings for inclusion in the report.
3. I/O Subsystem and Simulation Setup (November 21 – November 28)
1.
Design the I/O Subsystem:
· Use memory-mapped addresses for input/output devices (e.g., 0xFC for input, 0xFD for output).
· Decide on a
polling or
interrupt-driven method to handle I/O (interrupts are optional for this project).
1.
Integrate I/O Logic with the Processor:
· Write code to handle input from or output to the I/O device, depending on the memory address accessed.
· If using polling, ensure the CPU continuously checks I/O device status at set intervals.
1.
Set Up the Simulation Environment:
· Choose a simulation tool like
Logisim or
Verilog. Create and test each component separately (e.g., pipeline stages, memory, cache, I/O) and integrate them progressively.
1.
Simulate with Sample Programs:
· Develop sample programs in assembly language to test each functionality: pipeline execution, memory access, and I/O operations.
· Verify that the pipelined processor, cache, and I/O handle instructions as expected.
1.
Document: Record details about the I/O subsystem, simulation setup, and initial test results.
4. Performance Analysis (November 28 – December 1)
1.
Measure CPI (Cycles Per Instruction):
· Run test programs with and without pipelining to calculate the CPI.
· Use formulas like: CPI=Base CPI+(Stall Penalty×%Stalls)+(Branch Penalty×%Branches)
1.
Analyze Cache Performance:
· Measure cache hit and miss rates by running memory-intensive programs.
· Calculate
Average Memory Access Time (AMAT): AMAT=(Hit Rate×Cache Access Time)+(Miss Rate×Miss Penalty)
1.
Evaluate I/O Performance:
· Record CPU utilization with polling (and interrupts if implemented) to analyze the I/O system’s impact on performance.
1.
Compile Data:
· Organize data into tables or graphs for easy comparison.
· Prepare an analysis of results for CPI, cache performance, and I/O efficiency.
1.
Document: Complete the performance section of the report, summarizing results and insights on the system’s efficiency.
4. Final Report and Presentation (December 1 – December 3)
1.
Finalize the Processor Design Report:
· Complete all sections: architecture, pipeline stages, cache design, I/O subsystem, and performance analysis.
· Ensure clarity and thorough explanations, including diagrams and graphs.
1.
Prepare Simulation Code for Submission:
· Confirm that all simulation files (Logisim or HDL files) and test programs are correctly organized and functional.
· Include instructions for running the simulations.
1.
Develop a Presentation:
· Create a concise, 10-15 minute presentation that highlights the design, simulation results, and performance analysis.
· Use diagrams for each pipeline stage, cache structure, and memory hierarchy.
· Include graphs and tables of CPI, cache hit rates, and I/O impact for visual impact.
1.
Rehearse the Presentation:
· Practice explaining the project flow, design choices, and key findings to ensure a clear, confident delivery.
